1. Field of Invention
The present invention relates to a switching regulator with improved light load efficiency and mode transition characteristic, and a control circuit and a control method therefor; particularly, it relates to a switching regulator capable of performing proper mode switching control without requiring an input voltage signal or an output voltage signal, and a control circuit and a control method therefor.
2. Description of Related Art
There are many types of switching regulators, such as buck converter, boost converter, inverter converter, and buck-boost converter, etc. The aforementioned regulators can also be divided into synchronous and asynchronous types. There are two (four for buck-boost converter) power transistor switches in the synchronous switching regulators, and one of the power transistor switches is replaced by a diode in the non-synchronous regulators. By way of example, FIG. 1 shows a synchronous buck converter 1 which includes two power transistor switches Q1 and Q2, controlled by a control circuit 10. The control circuit 10 generates control signals according to a feedback signal FB obtained from the output Vout, and the transistor switches Q1 and Q2 are controlled by the control signals to convert electrical power from an input Vin to an output Vout. FIGS. 2-4 show a boost converter 2, an inverter converter 3, and a buck-boost converter 4, respectively. Though the circuit architecture and the number of transistors are different, these circuits operate under the same mechanism: The control circuit 10 generates control signals according to the feedback signal FB, and the power transistor switches operate to convert the electrical power from the input Vin to the output Vout according to the control signals.
In the aforementioned switching regulators, there is a light load efficiency issue if the power transistor switches still operate in the pulse width modulation (PWM) mode in light load condition (“light load” means that the load current, i.e., current supplied to a load circuit, is relatively low). Taking a voltage mode synchronous buck converter as an example, referring to FIG. 5, the control circuit 10 includes an error amplifier 12, a PWM comparator 16, and a driver stage 18. The error amplifier 12 generates an error amplification signal Comp by comparing the feedback signal FB with a reference signal Vref. The PWM comparator 16 generates a duty signal by comparing the error amplification signal Comp with a ramp signal Ramp. The driver stage 18 drives power transistor switches according to the duty signal. Referring to FIGS. 5 and 6, when the load current decreases, if the control circuit 10 is still operating in continuous conduction mode (CCM), the low gate transistor current could be less than zero and under such circumstance power is transmitted from the output back to the input, causing efficiency loss in power conversion. Thus, in light load condition, the low gate transistor should operate in a manner similar to a diode in an asynchronous converter, i.e., the so-called diode emulated mode, such that the regulator enters discontinuous conduction mode (DCM). When the regulator enters DCM from CCM, the voltage COMP decreases as the load current decreases, and the pulse width of the signal Duty decreases as well. However, if the load current decreases to an extent that the pulse width of the signal Duty becomes lower than a specific width, the power converted from the input to the output will be extremely limited, but the switching loss to operate the up and low gate transistors each time remains unchanged. A power conversion inefficiency issue thus occurs. Moreover, when the load condition changes, requiring the regulator to return to CCM from DCM, because the signal COMP stays at a very low level in DCM, it needs more time to return to a higher level in CCM. The response time is slow, i.e., the mode transition characteristic is poor, causing a deeper undershoot of the output voltage.
In view of the foregoing, U.S. Pat. No. 6,396,252 discloses a solution. The circuit shown in the original drawings of this patent is complicated, which is shown in FIG. 7 of this specification in a simplified form. This patent provides another circuit to generate a minimum pulse width Min_Duty. A logic circuit 17 selects the wider one between the minimum pulse width Min_Duty and the signal Duty, and outputs it to a driver stage 18. In this prior art, a scale circuit 11 obtains a specific ratio of the signal Vout, and a ramp generator 13 generates a signal Ramp_2 which is proportional to the input voltage Vin; the ratio of the signal Vout and the signal Ramp_2 is compared in a PWM comparator 15 to generate the minimum pulse width Min_Duty.
In the aforementioned prior art U.S. Pat. No. 6,396,252, the minimum pulse width Min_Duty is determined directly. This prior art has the following drawbacks: The input voltage Vin is essential to the circuit for generating the signal Ramp_2; the output voltage Vout is essential to the circuit for determining the minimum pulse width Min_Duty; an extra PWM comparator is essential; furthermore, the poor mode transition efficiency issue is not solved, i.e., the level of the signal COMP is too low in DCM that the response time is slow when the circuit switches from DCM to CCM.
U.S. Pat. No. 7,456,624 discloses a method and a circuit for entering the pulse skipping mode. Not many circuit details are disclosed in this patent, but it can be understood from its specification and figures that this prior art also needs the input voltage Vin and the output voltage Vout for mode control operation. The requirements for the input voltage Vin and the output voltage Vout are disadvantageous because more pins and more high voltage devices are required in an integrated circuit.
In view of the above drawbacks, it is desired to provide a switching regulator with improved mode transition efficiency, which does not require an input voltage signal or an output voltage signal for mode control, and a control circuit and a control method therefor.